The present invention relates to a DLL circuit, and an imaging device and a memory device each including the DLL circuit, and particularly relates to a function for suppressing transition to an improper lock state.
FIG. 16 illustrates the configuration of a typical DLL circuit. In the DLL circuit, an input clock CKin is successively delayed by n delay elements 900, 900, . . . which form a variable delay circuit 90, thereby generating n delayed clocks CK(1), CK(2), . . . , CK(n) having different phases. A frequency phase comparison circuit 91 compares the phases of the delayed clocks CK(1) and CK(n) based on the timings of the occurrences of rising edges of the delayed clocks CK(1) and CK(n) and outputs a charge signal UP or a discharge signal DN according to the comparison result. In response to the charge signal UP or the discharge signal DN, a charge pump circuit 92 charges or discharges the output voltage of a low-pass filter 93. An increase/decrease in the output voltage of the low-pass filter 93 causes a decrease/increase in delay time in each of the delay elements 900, 900, . . . . In this way, the delay times in the delay elements 900, 900, . . . are increased or decreased in accordance with the phase comparison result, whereby the phases of the delayed clocks CK(1) and CK(n) are locked.
In the DLL circuit, it is important to lock the phases of the delayed clocks CK(1) and CK(n) in a state in which the difference in delay time between the delayed clocks CK(1) and CK(n) is one cycle of the delayed clock CK(1). However, in the DLL circuit, since it is not possible to identify the difference in delay time between the delayed clocks CK(1) and CK(n), the phases of the delayed clocks CK(1) and CK(n) are sometimes locked in a state in which the difference in delay time between the delayed clocks CK(1) and CK(n) is not equal to one cycle (for example, an integral number of cycles greater than 1). To deal with this, typically, the delay times in the delay elements 900 are set to a minimum when phase adjustments are started in the DLL circuit, and then the delay times in the delay elements 900 are controlled in such a manner that the difference in delay time between the delayed clocks CK(1) and CK(n) is gradually increased. By doing such control as this, a proper lock state (i.e., a phase state in which the phases of the delayed clocks CK(1) and CK(n) are locked, and the difference in delay time between the delayed clocks CK(1) and CK(n) is one cycle) is achieved.
Japanese Laid-Open Publication No. 2005-20711 (Patent Document 1) discloses a DLL circuit in which a circuit for detecting an improper lock state (i.e., a phase state in which the phases of the delayed clocks CK(1) and CK(n) are locked, but the difference in delay time between the delayed clocks CK(1) and CK(n) is not one cycle) is provided, and when the improper lock state is detected, delay times in delay elements are minimized.
In the conventional DLL circuit, the frequency phase comparison circuit 91 performs the phase comparison based on the timings of the occurrences of edges of the delayed clocks CK(1) and CK(n). Therefore, when the clock waveforms are disturbed (such as in the case of the presence of disturbance noise or in a case in which the supply of the input clock CKin is temporarily stopped and then started again), at a time t1, the rising edge of the delayed clock CK(1) does not occur, and thus only the rising edge of the delayed clock CK(n) occurs as shown in FIG. 17. Consequently, the discharge signal DN continues to be output until the next rising edge of the delayed clock CK(1) occurs at a time t2. The longer the time interval during which the discharge signal DN is output, the more excessive the delay times in the delay elements 900, 900, . . . . As a result, the difference in delay time between the delayed clocks CK(1) and CK(n) becomes greater than required, and hence the improper lock state is likely to occur as shown at a time t3 in FIG. 17.
Also, in the DLL circuit described in Patent Document 1, since the delay time in each of the delay elements 900, 900, . . . is set to a minimum so as to terminate the improper lock state, the process of gradually increasing the delay times in the delay elements 900, 900, . . . must be performed again from the beginning, and thus the time (the recovery time) required for stabilizing the phase state of the delayed clocks CK(1) and CK(n) in the proper lock state is extended.